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| SM320F2812-HT Datasheet, PDF (99/155 Pages) Texas Instruments – Digital Signal Processor | |||
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www.ti.com
XCLKIN
SM320F2812-HT
SGUS062A â JUNE 2009 â REVISED APRIL 2010
X1
XCLKOUT
XRS
Address/Data/
Control
XF/XPLLDIS
XMP/MC
(XCLKIN * 5)
User-Code Execution
GPIOF14/XF
(Donât Care)
tw(RSL2)
td(EX)
(Donât Care)
tsu(XPLLDIS)
(Donât Care)
XPLLDIS Sampling
th(XMP/MC)
XCLKIN/8
User-Code Dependent
User-Code Execution Phase
th(XPLLDIS)
GPIOF14
User-Code Dependent
(Donât Care)
Boot-Mode Pins
Peripheral/GPIO Function
Boot-ROM Execution Starts
GPIO Pins as Input
th(boot-mode) (see Note A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT is based on user environment and could be with or without PLL enabled.
Figure 6-11. Warm Reset in Microcomputer Mode
X1/XCLKIN
SYSCLKOUT
Write to PLLCR
XCLKIN x 2
XCLKIN/2
XCLKIN x 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 XCLKIN Cycles Long.)
(Changed CPU Frequency)
Figure 6-12. Effect of Writing Into PLLCR Register
Copyright © 2009â2010, Texas Instruments Incorporated
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Electrical Specifications
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