SM320F2812-HT Datasheet, PDF (47/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13.
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers⁽¹⁾
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
reserved
0x00 7010
0x00 7017
8
reserved
0x00 7018
1
reserved
0x00 7019
1
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low Power Mode Control Register 1
reserved
PLLCR
0x00 7020
0x00 7021
1
1
PLL Control Register⁽²⁾
SCSR
0x00 7022
1
System Control & Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
reserved
0x00 7024
1
WDKEY
0x00 7025
1
Watchdog Reset Key Register
reserved
0x00 7026
0x00 7028
3
WDCR
0x00 7029
1
Watchdog Control Register
reserved
0x00 702A
0x00 702F
6
(1) All of the above registers can only be accessed by executing the EALLOW instruction.
(2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
does not reset PLLCR.
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