SM320F2812-HT Datasheet, PDF (129/155 Pages) Texas Instruments – Digital Signal Processor

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SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
See
Notes A
and B
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
XRD
XWE
XR/W
t_{d(XCOH-XRNWL)}
XD[0:15]
t_en(XD)XWEL
WS (Synch)
Active
t_{d(XCOHL-XWEL)}
t_d(XWEL-XD
)
Trail
See Note C
t_{d(XCOHL-XZCSH)}
t_{h(XRDYsynchH)XZCSH}
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
DOUT
t_dis(XD)XRNW
t_h(XD)XWEH
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{e(XRDYsynchH)}
t_{su(XRDHsynchH)XCOHL}
XREADY(Synch)
See Note D
Legend:
See Note E
= Don’t care. Signal can be high or low during this time.
NOTES:
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access
to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) t_c(XTIM) − t_{su(XRDYsynchL)XCOHL}
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) t_c(XTIM)
Figure 6-33. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
N/A ⁽¹⁾
N/A ⁽¹⁾
N/A ⁽¹⁾
1
0
XWRLEAD
≥1
(1) N/A = "Don't care" for this example
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
0 = XREADY
(Synch)
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Electrical Specifications 129