SM320F2812-HT Datasheet, PDF (123/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
≥1
≥0
≥0
0
0
(1) N/A = "Don't care" for this example
XWRLEAD
N/A ⁽¹⁾
XWRACTIVE XWRTRAIL READYMODE
N/A ⁽¹⁾
N/A ⁽¹⁾
N/A ⁽¹⁾
6.24 External Interface Write Timing
Table 6-36. External Memory Interface Write Switching Characteristics⁽¹⁾
PARAMETER
MIN
MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
td(XCOH-XA)
t_{d(XCOHL-XWEL)}
t_{d(XCOHL-XWEH)}
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XRNWH)}
t_en(XD)XWEL
t_d(XWEL-XD)
t_h(XA)XZCSH
t_h(XD)XWE
t_dis(XD)XRNW
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
–2
–2
0
TW–2 ⁽³⁾
4
1 ns
3 ns
2 ns
2 ns
2 ns
1 ns
1 ns
ns
4 ns
(2)_ns
ns
ns
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3) TW = Trail period, write access. See Table 6-25 .
Lead
Active
Trail
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XZCSH)}
t_{d(XCOH-XRNWL)}
t_d(XWEL-XD)
t_en(XD)XWEL
t_{d(XCOHL-XWEL)}
DOUT
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
t_dis(XD)XRNW
t_h(XD)XWEH
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-30. Example Write Access
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Electrical Specifications 123