SM320F2812-HT Datasheet, PDF (50/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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• C_L1 = C_L2 = 24 pF
• C_shunt = 6 pF
• ESR range = 25 to 40 Ω
3.11 Watchdog Block
The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog
counter. Figure 3-9 shows the various functional blocks within the watchdog module.
OSCCLK
WDCR (WDPS(2:0))
WDCR (WDDIS)
Watchdog ^WDCLK
/512
Prescaler
WDCNTR(7:0)
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
XRS
WDKEY(7:0)
Watchdog
55 + AA
Key Detector
Bad Key
Good Key
Core-reset
WDCR (WDCHK(2:0))
Bad
WDCHK
Key
WDRST
Generate
Output Pulse _WDINT
(512 OSCCLKs)
SCSR (WDENINT)
WDRST
(See Note A)
101
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-9. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module runs off the PLL clock or the oscillator clock. The
WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See
Section 3.12, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
50
Functional Overview
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