SM320F2812-HT Datasheet, PDF (127/155 Pages) Texas Instruments – Digital Signal Processor

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SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
See Notes
A and B
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
XREADY(Asynch)
Lead
WS (Asynch)
Active
Trail
See Note C
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_{d(XCOHL-XRDH)}
t_a(A)
t_h(XD)XRD
DIN
t_{su(XRDYasynchL)XCOHL}
t_{e(XRDYasynchH)}
t_{h(XRDYasynchL)}
t_{h(XRDYasynchH)XZCSH}
t_{su(XRDYasynchH)XCOHL}
See Note D
Legend:
See Note E
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always hold sthe last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) t_c(XTIM) − t_{su(XRDYasynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE −2) t_c(XTIM)
Figure 6-32. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
≥1
3
≥1
1
0
XWRLEAD
N/A ⁽¹⁾
(1) N/A = "Don't care" for this example
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
READYMODE
1 = XREADY
(Asynch)
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Electrical Specifications 127