SM320F2812-HT Datasheet, PDF (72/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 4-7. McBSP Register Summary (continued)
NAME
ADDRESS
0x00 78xxh
DRR2
00
DRR1
01
DXR2
02
DXR1
03
MFFTX
20
MFFRX
21
MFFCT
22
MFFINT
23
MFFST
24
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers⁽¹⁾
R
0x0000
McBSP Data Receive Register 2 – Top of receive FIFO
–Read First FIFO pointers does not advance
R
0x0000
McBSP Data Receive Register 1 – Top of receive FIFO
–Read Second for FIFO pointers to advance
W
0x0000
McBSP Data Transmit Register 2 – Top of transmit FIFO
–Write First FIFO pointers does not advance
W
0x0000
McBSP Data Transmit Register 1 – Top of transmit FIFO
–Write Second for FIFO pointers to advance
FIFO Control Registers
R/W
0xA000
McBSP Transmit FIFO Register
R/W
0x201F
McBSP Receive FIFO Register
R/W
0x0000
McBSP FIFO Control Register
R/W
0x0000
McBSP FIFO Interrupt Register
R/W
0x0000
McBSP FIFO Status Register
(1) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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