SM320F2812-HT Datasheet, PDF (6/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6-23 General-Purpose Input Timing ................................................................................................ 109
6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 110
6-25 SPI Master External Timing (Clock Phase = 1)............................................................................. 112
6-26 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 114
6-27 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 116
6-28 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 120
6-29 Example Read Access ......................................................................................................... 122
6-30 Example Write Access ......................................................................................................... 124
6-31 Example Read With Synchronous XREADY Access ...................................................................... 126
6-32 Example Read With Asynchronous XREADY Access ..................................................................... 127
6-33 Write With Synchronous XREADY Access.................................................................................. 129
6-34 Write With Asynchronous XREADY Access ................................................................................ 130
6-35 External Interface Hold Waveform............................................................................................ 132
6-36 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 133
6-37 ADC Analog Input Impedance Model ........................................................................................ 137
6-38 ADC Power-Up Control Bit Timing ........................................................................................... 137
6-39 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 139
6-40 Simultaneous Sampling Mode Timing ....................................................................................... 140
6-41 McBSP Receive Timing........................................................................................................ 144
6-42 McBSP Transmit Timing ....................................................................................................... 144
6-43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 145
6-44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 146
6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 147
6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 148
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List of Figures
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