SM320F2812-HT Datasheet, PDF (110/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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NOTE
Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than
the I/O buffer speed limit (20 MHz).
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
3
4
5
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISTE
(see Note A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-24. SPI Master Mode External Timing (Clock Phase = 0)
110 Electrical Specifications
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