SM320F2812-HT Datasheet, PDF (30/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows
the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on
reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in
software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are
affected by XMP/MC.
I/O space is not supported on the F2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3-2.
Table 3-2. Wait States
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Peripheral Frame 2
L0 and L1 SARAMs
OTP (or ROM)
Flash (or ROM)
H0 SARAM
Boot-ROM
XINTF
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
Programmable,
1-wait minimum
Programmable,
0-wait minimum
0-wait
1-wait
Programmable,
1-wait minimum
Fixed
Fixed
Fixed
Fixed
COMMENTS
Programmed via the Flash registers. 1-wait-state operation is possible at a reduced
CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information.
Programmed via the Flash registers. 0-wait-state operation is possible at reduced
CPU frequency. The CSM password locations are hardwired for 16 wait-states.
See Section 3.2.6, Flash (F281x Only), for more information.
Fixed
Fixed
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
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Functional Overview
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