SM320F2812-HT Datasheet, PDF (119/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
or
Table 6-31. XTIMING Register Configuration Restrictions^{(1) (2)}
XRDLEAD
XRDACTIVE
XRDTRAIL
≥2
≥1
0
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XWRLEAD
≥2
XWRACTIVE
≥1
Examples of valid and invalid timing when using Asynchronous XREADY:
Table 6-32. Asynchronous XREADY^{(1) (2)}
XWRTRAIL
0
X2TIMING
0, 1
Invalid
Invalid
Invalid
Valid
Valid
Valid
XRDLEAD
0
1
1
1
1
2
XRDACTIVE
0
0
1
1
2
1
XRDTRAIL
0
0
0
0
0
0
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XWRLEAD
0
1
1
1
1
2
XWRACTIVE
0
0
1
1
2
1
XWRTRAIL
0
0
0
0
0
0
X2TIMING
0, 1
0, 1
0
1
0, 1
0, 1
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-33.
MODE
1
Example:
2
Example:
3
Example:
4
Example:
Table 6-33. XINTF Clock Configurations
SYSCLKOUT
150 MHz
150 MHz
150 MHz
150 MHz
XTIMCLK
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
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Electrical Specifications 119