SM320F2812-HT Datasheet, PDF (101/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6-11. STANDBY Mode Switching Characteristics⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
t_d(IDLE-XCOH)
Delay time, IDLE instruction
executed to XCLKOUT high
32 × t_c(SCO)
12 × t_c(CI)
Cycles
t_w(WAKE-INT)
Pulse duration, external
wake-up signal
Without input
qualifier
With input qualifier
Delay time, external wake
signal to program execution
resume ⁽³⁾
12 × t_c(CI)
(2 + QUALSTDBY)⁽²⁾ × t_c(CI)
Cycles
Cycles
–Wake-up from Flash
–Flash module in active
state
Without input
qualifier
12 × t_c(CI)
Cycles
t_d(WAKE-STBY)
–Wake-up from Flash
–Flash module in active
state
–Wake-up from Flash
–Flash module in sleep
state
With input qualifier
Without input
qualifier
12 × t_c(CI) + t_w(WAKE-INT)
1125 × t_c(SCO)
Cycles
Cycles
–Wake-up from Flash
–Flash module in sleep
state
With input qualifier
1125 × t_c(SCO) + t_w(WAKE-INT)
Cycles
–Wake-up from SARAM
Without input
qualifier
12 x tc(CI)
Cycles
–Wake-up from SARAM With input qualifier
12 × t_c(CI) + t_w(WAKE-INT)
Cycles
(1) Not production tested.
(2) QUALSTDBY is a 6-bit field in the LPMCR0 register.
(3) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
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