 English |
|
|
|
|
|
|
|
| SM320F2812-HT Datasheet, PDF (68/155 Pages) Texas Instruments – Digital Signal Processor | |||
| |||
| ◁ |
SM320F2812-HT
SGUS062A â JUNE 2009 â REVISED APRIL 2010
www.ti.com
The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-6. CAN Registers Map(1)
REGISTER NAME
ADDRESS
CANME
0x00 6000
CANMD
0x00 6002
CANTRS
0x00 6004
CANTRR
0x00 6006
CANTA
0x00 6008
CANAA
0x00 600A
CANRMP
0x00 600C
CANRML
0x00 600E
CANRFP
0x00 6010
CANGAM
0x00 6012
CANMC
0x00 6014
CANBTC
0x00 6016
CANES
0x00 6018
CANTEC
0x00 601A
CANREC
0x00 601C
CANGIF0
0x00 601E
CANGIM
0x00 6020
CANGIF1
0x00 6022
CANMIM
0x00 6024
CANMIL
0x00 6026
CANOPC
0x00 6028
CANTIOC
0x00 602A
CANRIOC
0x00 602C
CANTSC
0x00 602E
CANTOC
0x00 6030
CANTOS
0x00 6032
(1) These registers are mapped to Peripheral Frame 1.
SIZE (Ã32)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
Mailbox enable
Mailbox direction
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
Bit-timing configuration
Error and status
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
68
Peripherals
Copyright © 2009â2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese