SM320F2812-HT Datasheet, PDF (128/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6-41. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)⁽¹⁾
PARAMETER
MIN MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XWEL)}
t_{d(XCOHL-XWEH)}
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XRNWH)}
t_en(XD)XWEL
t_d(XWEL-XD)
t_h(XA)XZCSH
t_h(XD)XWE
t_dis(XD)XRNW
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
–2
–2
0
(2)
TW–2 ⁽³⁾
4
1
ns
3
ns
2
ns
2
ns
2
ns
1
ns
1
ns
ns
4
ns
ns
ns
ns
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3) TW = trail period, write access (see Table 6-25 )
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)^{(1) (2)}
MIN MAX UNIT
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{e(XRDYsynchH)}
t_{su(XRDYsynchH)XCOHL}
t_{h(XRDYsynchH)XZCSH}
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
15
ns
12
ns
3 ns
15
ns
0
ns
(1) Not production tested.
(2) The first XREADY (Synch) sample occurs with respect to E in Figure 6-33 :
E =(XWRLEAD + XWRACTIVE) t_c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each t_c(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE + n – 1) t_c(XTIM) – t_{su(XRDYsynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)^{(1) (2)}
MIN MAX UNIT
t_{su(XRDYasynchL)XCOHL}
t_{h(XRDYasynchL)}
t_{e(XRDYasynchH)}
t_{su(XRDYasynchH)XCOHL}
t_{h(XRDYasynchH)XZCSH}
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
11
ns
8
ns
3 ns
11
ns
0
ns
(1) Not production tested.
(2) The first XREADY (Synch) sample occurs with respect to E in Figure 6-33:
E = (XWRLEAD + XWRACTIVE – 2) t_c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it is
sampled again each t_c(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) t_c(XTIM) – t_{su(XRDYasynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
128 Electrical Specifications
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