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SM320F2812-HT Datasheet, PDF (143/155 Pages) Texas Instruments – Digital Signal Processor
SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-53. McBSP Switching Characteristics(1) (2) (3)
NO.
PARAMETER
MIN
MAX UNIT
M1 tc(CKRX)
M2 tw(CKRXH)
M3 tw(CKRXL)
M4 td(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
2P
ns
CLKR/X int
D – 5 (4) D + 5(4)
ns
CLKR/X int
C – 5(4) C + 5(4)
ns
CLKR int
CLKR ext
0
4
ns
3
27
M5 td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
CLKX ext
0
4
ns
3
27
M6 tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance following last CLKX int
data bit
CLKX ext
8
ns
14
Delay time, CLKX high to DX valid.
CLKX int
9
This applies to all bits except the first bit transmitted.
CLKX ext
28
M7 td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
DXENA = 0
CLKX ext
8
ns
14
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
DXENA = 1
CLKX int
CLKX ext
P+8
P + 14
CLKX int
0
Enable time, CLKX high to DX driven
DXENA = 0
CLKX ext
6
M8 ten(CKXH-DX)
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
DXENA = 1
CLKX int
CLKX ext
P
P+6
ns
M9 td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY= 00b) mode.
DXENA = 1
FSX int
FSX ext
FSX int
FSX ext
8
14
ns
P+8
P + 14
FSX int
0
Enable time, FSX high to DX driven
DXENA = 0
FSX ext
6
M10 ten(FXH-DX)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY= 00b) mode
DXENA = 1
FSX int
FSX ext
P
P+6
ns
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns
(3) Not production tested.
(4) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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Electrical Specifications 143