SM320F2812-HT Datasheet, PDF (118/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-28. XTIMING Register Configuration Restrictions^{(1) (2)}
XRDLEAD
XRDACTIVE
XRDTRAIL
≥1
≥1
≥0
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XWRLEAD
≥1
XWRACTIVE
≥1
Examples of valid and invalid timing when using Synchronous XREADY:
XWRTRAIL
≥0
Table 6-29. Valid and Invalid Timing when using Synchronous XREADY^{(1) (2)}
X2TIMING
0, 1
Invalid
Invalid
Valid
XRDLEAD
0
1
1
XRDACTIVE
0
0
1
XRDTRAIL
0
0
0
XWRLEAD
0
1
1
XWRACTIVE
0
0
1
XWRTRAIL
0
0
0
X2TIMING
0, 1
0, 1
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
• If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1),
then:
1. Lead:
2. Active:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
AR ≥ 2 × t_c(XTIM)
AW ≥ 2 × t_c(XTIM)
NOTE
Restriction does not include external hardware wait states
3. Lead + Active:
LR + AR ≥ 4 × t_c(XTIM)
LW + AW ≥ 4 × t_c(XTIM)
NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-30. XTIMING Register Configuration Restrictions^{(1) (2)}
XRDLEAD
≥1
XRDACTIVE
≥2
XRDTRAIL
0
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XWRLEAD
≥1
XWRACTIVE
≥2
XWRTRAIL
0
X2TIMING
0, 1
118 Electrical Specifications
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