SM320F2812-HT Datasheet, PDF (100/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.15 Low-Power Mode Wakeup Timing
Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6-10. IDLE Mode Switching Characteristics⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t_w(WAKE-INT)
Pulse duration, external wake-up
signal
Delay time, external wake signal
to program execution resume⁽³⁾
Without input qualifier
With input qualifier
2 x t_c(SCO)
1 × t_c(SCO) + IQT ⁽²⁾
Cycles
Cycles
–Wake-up from Flash
–Flash module in active state
Without input qualifier
8 × t_c(SCO)
Cycles
t_d(WAKE-IDLE)
– Wake-up from Flash
–Flash module in active state
–Wake-up from Flash
–Flash module in sleep state
With input qualifier
Without input qualifier
8 × t_c(SCO) + IQT ⁽²⁾
1050 × t_c(SCO)
Cycles
Cycles
–Wake-up from Flash
–Flash module in sleep state
With input qualifier
1050 × t_c(SCO) + IQT⁽²⁾
Cycles
–Wake-up from SARAM
–Wake-up from SARAM
Without input qualifier
With input qualifier
8 × t_c(SCO)
8 × t_c(SCO) + IQT ⁽²⁾
Cycles
Cycles
(1) Not production tested.
(2) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × t_c(SCO)
(3) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
A0−A15
t_{d(WAKE−IDLE)}
XCLKOUT
(see Note A)
WAKE INT
(see Note B)
t_{w(WAKE−INT)}
A. XCLKOUT = SYSCLKOUT
B. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-13. IDLE Entry and Exit Timing
100 Electrical Specifications
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