SM320F2812-HT Datasheet, PDF (145/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
6.30.2 McBSP as SPI Master or Slave Timing
Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
NO.
M30 t_su(DRV0CKXL)
Setup time, DR valid before CLKX low
M31 t_h(CKXL0DRV)
Hold time, DR valid after CLKX low
M32 t_{su(BFXL0CKXH)} Setup time, FSX low before CLKX high
M33 t_c(CKX)
Cycle time, CLKX
(1) Not production tested.
MASTER
MIN MAX
P – 10
P – 10
2P
SLAVE
MIN MAX
8P – 10
8P – 10
8P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)^{(1) (2)}
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
M24 t_h(CKXL0FXL)
Hold time, FSX low after CLKX low
2P
ns
M25 t_d(FXL0CKXH)
Delay time, FSX low to CLKX high
P
ns
M28 t_{dis(FXH0DXHZ)}
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
ns
M29 t_d(FXL0DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns.
CLKX
FSX
DX
DR
LSB
M32
MSB
M33
M24
M25
M28
M29
Bit 0
Bit 0
Bit(n-1)
(n-2)
M30
M31
(n-3)
(n-4)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Electrical Specifications 145