SM320F2812-HT Datasheet, PDF (94/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.12 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the F2812 DSP. Table 6-3 lists the cycle times of various clocks.
Table 6-3. Clock Table and Nomenclature
MIN
NOM MAX
On-chip oscillator clock
t_c(OSC), Cycle time
Frequency
28.6
50
20
35
XCLKIN
t_c(CI), Cycle time
Frequency
6.67
250
4
150
SYSCLKOUT
t_c(SCO), Cycle time
Frequency
6.67
500
2
150
XCLKOUT
HSPCLK
LSPCLK
ADC clock
t_c(XCO), Cycle time
Frequency
t_c(HCO), Cycle time
Frequency
t_c(LCO), Cycle time
Frequency
t_c(ADCCLK), Cycle time ⁽²⁾
Frequency
6.67
0.5
6.67
13.3
40
13.3 ⁽¹⁾
75 ⁽¹⁾
26.6 ⁽¹⁾
37.5 ⁽¹⁾
2000
150
150
75
25
SPI clock
t_c(SPC), Cycle time
Frequency
50
20
McBSP
t_c(CKG), Cycle time
Frequency
50
20
XTIMCLK
t_c(XTIM), Cycle time
Frequency
6.67
150
(1) This is the default reset value if SYSCLKOUT = 150 MHz.
(2) The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
UNIT
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
6.13 Clock Requirements and Characteristics
6.13.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-4. Input Clock Frequency⁽¹⁾
PARAMETER
f_x
Input clock frequency
f_l
Limp mode clock frequency
(1) Not production tested.
(2) Not guaranteed for T_A > 125°C.
Resonator ⁽²⁾
Crystal ⁽²⁾
XCLKIN
MIN TYP
20
20
4
MAX
35
35
150
2
UNIT
MHz
MHz
94
Electrical Specifications
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