SM320F2812-HT Datasheet, PDF (36/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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3.2.20 Serial Port Peripherals
The F2812 supports the following serial communication peripherals:
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
:
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO.
This significantly reduces the overhead for servicing this peripheral.
SPI:
SCI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between
the DSP controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers,
display drivers, and ADCs. Multi-device communications are supported by the
master/slave operation of the SPI. On the F2812, the port supports a 16-level receive
and transmit FIFO for reducing servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F2812, the port supports a 16-level receive and transmit FIFO
for reducing servicing overhead.
3.3 Register Map
The F2812 device contains three peripheral register spaces. The spaces are categorized as follows:
• Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See
Table 3-4.
• Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-5.
• Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-6.
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Functional Overview
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