SM320F2812-HT Datasheet, PDF (137/155 Pages) Texas Instruments – Digital Signal Processor

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R_s
ADCIN0
Source
ac
Signal
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
R_on
1 kΩ
Switch
C_p
10 pF
C_h
1.25 pF
Typical Values of the Input Circuit Components:
Switch Resistance (R_on):
Sampling Capacitor (C_h):
Parasitic Capacitance (C_p):
Source Resistance (R_s):
1 kΩ
1.25 pF
10 pF
50 Ω
Figure 6-37. ADC Analog Input Impedance Model
28x DSP
6.29.4 ADC Power-Up Control Bit Timing
PWDNBG
ADC Power Up Delay
ADC Ready for Conversions
PWDNREF
PWDNADC
Request for
ADC
Conversion
t_d(BGR)
t_d(PWD)
Figure 6-38. ADC Power-Up Control Bit Timing
Table 6-49. ADC Power-Up Delays^{(1) (2)}
MIN TYP MAX UNIT
t_d(BGR)
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the ADCPWDN bit is enabled.
7
8
10 ms
t_d(PWD)
Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register (ADCPWDN)
is to be set to 1 before any ADC conversions are initiated.
20
50
ms
1 ms
(1) These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If
conversions are started without these delays, the ADC results shows a higher gain. For power down, all three bits can be cleared at the
same time.
(2) Not production tested.
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Electrical Specifications 137