SM320F2812-HT Datasheet, PDF (139/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-50. Sequential Sampling Mode Timing⁽¹⁾
SAMPLE n
t_d(SH)
Delay time from event trigger to
sampling
t_SH
Sample/Hold width/Acquisition width
t_{d(schx_n)}
t_{d(schx_n+1)}
Delay time for first result to appear
in the Result register
Delay time for successive results to
appear in the Result register
(1) Not production tested.
2.5t_c(ADCCLK)
(1 + Acqps) ×
t_c(ADCCLK)
4t_c(ADCCLK)
SAMPLE n + 1
AT 25–MHz ADC
CLOCK,
t_c(ADCCLK) = 40 ns
REMARKS
(2 + Acqps) ×
t_c(ADCCLK)
40 ns with Acqps = 0
Acqps value = 0-15
ADCTRL1[8:11]
160 ns
80 ns
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Electrical Specifications 139