SM320F2812-HT Datasheet, PDF (95/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled⁽¹⁾
NO.
C8
t_c(CI)
C9
t_f(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
C10 t_r(CI)
Rise time, XCLKIN
C11 t_w(CIL)
Pulse duration, X1/XCLKIN low as a percentage of t_c(CI)
C12 t_w(CIH)
Pulse duration, X1/XCLKIN high as a percentage of t_c(CI)
(1) Not production tested.
Up to 30 MHz
30 MHz to 150 MHz
Up to 30 MHz
30 MHz to 150 MHz
Table 6-6. XCLKIN Timing Requirements – PLL Disabled⁽¹⁾
MIN MAX
6.67 250
6
2
6
2
40
60
40
60
UNIT
ns
ns
ns
%
%
NO.
C8
t_c(CI)
C9
t_f(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Up to 30 MHz
30 MHz to 150 MHz
C10 t_r(CI)
Rise time, XCLKIN
Up to 30 MHz
30 MHz to 150 MHz
C11 t_w(CIL)
XCLKIN ≤ 120 MHz
Pulse duration, X1/XCLKIN low as a percentage of t_{c(CI) 120 < XCLKIN ≤ 150 MHz}
C12 t_w(CIH)
Pulse duration, X1/XCLKIN high as a percentage of
t_c(CI)
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
(1) Not production tested.
Table 6-7. Possible PLL Configuration Modes⁽¹⁾
MIN MAX UNIT
6.67
250 ns
6
ns
2
6
ns
2
40
60
%
45
55
40
60
%
45
55
PLL MODE
REMARKS
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the
CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin.
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed.
PLL Bypassed However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before
feeding it to the CPU.
PLL Enabled
Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now
divides the output of the PLL by two before feeding it to the CPU.
(1) Not production tested.
SYSCLKOUT
XCLKIN
XCLKIN/2
(XCLKIN × n)/2
6.13.2 Output Clock Characteristics
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)^{(1) (2)}
NO.
PARAMETER
MIN
C1
C3 ⁽⁴⁾
C4 ⁽⁴⁾
C5 ⁽⁴⁾
C6 ⁽⁴⁾
C7 ⁽⁴⁾
t_c(XCO)
t_f(XCO)
t_r(XCO)
t_w(XCOL)
t_w(XCOH)
t_p
Cycle time, XCLKOUT
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time⁽⁵⁾
6.67 ⁽³⁾
H–2
H–2
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5t_c(XCO)
(3) The PLL must be used for maximum frequency operation.
(4) Not production tested..
(5) This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
TYP
2
2
MAX
H+2
H+2
131 072t_c(CI)
UNIT
ns
ns
ns
ns
ns
ns
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