SM320F2812-HT Datasheet, PDF (46/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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3.7 System Control
This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-6 shows the various clock and reset domains in the F2812 device that are
discussed.
See Note A
A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3-6. Clock and Reset Domains
46
Functional Overview
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