SM320F2812-HT Datasheet, PDF (125/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
6.25 External Interface Ready-on-Read Timing With One External Wait State
Table 6-37. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)⁽¹⁾
PARAMETER
MIN MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_d(XCOHL-XRDH
t_h(XA)XZCSH
t_h(XA)XRD
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
1 ns
–2
3 ns
2 ns
1 ns
–2
1 ns
(2)
ns
(2)
ns
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-38. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)⁽¹⁾
t_a(A)
Access time, read data from address valid
t_a(XRD)
Access time, read data valid from XRD active low
t_su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
t_h(XD)XRD
Hold time, read data valid after XRD inactive high
(1) Not production tested.
(2) LR = Lead period, read access. AR = Active period, read access. See Table 6-25 .
MIN
MAX UNIT
(LR + AR) – 14⁽²⁾
ns
AR – 12⁽²⁾
ns
12
ns
0
ns
Table 6-39. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)^{(1) (2)}
MIN MAX UNIT
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{e(XRDYsynchH)}
t_{su(XRDYsynchH)XCOHL}
t_{h(XRDYsynchH)XZCSH}
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
15
ns
12
ns
3 ns
15
ns
0
ns
(1) Not production tested.
(2) The first XREADY (Synch) sample occurs with respect to E in Figure 6-31 :
E = (XRDLEAD + XRDACTIVE) t_c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each t_c(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) t_c(XTIM) – t_{su(XRDYsynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)^{(1) (2)}
t_{su(XRDYAsynchL)XCOHL}
t_{h(XRDYAsynchL)}
t_{e(XRDYAsynchH)}
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT
edge
MIN MAX UNIT
11
ns
8
ns
3 ns
(1) Not production tested.
(2) The first XREADY (Asynch) sample occurs with respect to E in Figure 6-32 :
E = (XRDLEAD + XRDACTIVE – 2) t_c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it wis
sampled again each t_c(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) t_c(XTIM) – t_{su(XRDYasynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
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