SM320F2812-HT Datasheet, PDF (126/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ^{(1) (2)}
(continued)
t_{su(XRDYAsynchH)XCOHL}
t_{h(XRDYasynchH)XZCSH}
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
MIN MAX UNIT
11
ns
0
ns
See Notes A and B
Lead
Active
WS (Synch)
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_a(A)
t_{su(XRDYsynchL)XCOHL}
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
t_h(XD)XRD
DIN
XREADY(Synch)
t_{h(XRDYsynchL)}
t_{su(XRDHsynchH)XCOHL}
See Note D
t_{e(XRDYsynchH)}
t_{h(XRDYsynchH)XZCSH}
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t_c(XTIM) − t_{su(XRDYsynchL)XCOHL}
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t_c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6-31. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
≥1
3
≥1
1
0
XWRLEAD
N/A ⁽¹⁾
(1) N/A = "Don't care" for this example
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
READYMODE
0 = XREADY
(Synch)
126 Electrical Specifications
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