SM320F2812-HT Datasheet, PDF (42/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
3.6 Interrupts
Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device.
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Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
INT1 to INT12
PIE
WAKEINT
WDINT
LPMINT
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
Watchdog
Low-Power Modes
XINT1
C28x CPU
INT14
INT13
NMI
TINT0
TINT2
TINT1
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
TIMER 0
TIMER 2 (for RTOS)
TIMER 1 (for RTOS)
XINT2
GPIO
MUX
select
enable
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
XNMI_XINT13
† _{Out of a possible 96 interrupts, 45 are currently used by peripherals.}
Figure 3-4. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F2812, 45 of these are used by peripherals as
shown in Table 3-10.
42
Functional Overview
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