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| SM320F2812-HT Datasheet, PDF (98/155 Pages) Texas Instruments – Digital Signal Processor | |||
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SM320F2812-HT
SGUS062A â JUNE 2009 â REVISED APRIL 2010
VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
VDD, VDD1 (1.8 V (or
1.9 V))
XCLKIN
2.5 V
0.3 V
X1
XCLKOUT
tOSCST
XCLKIN/8 (See Note A)
www.ti.com
User-Code Dependent
XRS
Address/Data/
Control
XF/XPLLDIS
XMP/MC
I/O Pins
tw(RSL)
td(EX)
(Donât Care)
XPLLDIS Sampling
(Donât Care)
tsu(XPLLDIS)
th(XMP/MC)
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
th(XPLLDIS)
GPIOF14/XF (User-Code Dependent)
(Donât Care)
User-Code Dependent
See Note B
Input Configuration (State Depends on Internal PU/PD)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
Figure 6-10. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
98
Electrical Specifications
Copyright © 2009â2010, Texas Instruments Incorporated
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