SM320F2812-HT Datasheet, PDF (105/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-13. PWM Switching Characteristics^{(1) (2)}
PARAMETER
TEST CONDITIONS
t_w(PWM) ^{(3) (4)}
Pulse duration, PWMx output high/low
t_d(PWM)XCO
Delay time, XCLKOUT high to PWMx output switching
XCLKOUT = SYSCLKOUT/4
(1) See the GPIO output timing for fall/rise times for PWM pins.
(2) PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
(3) PWM outputs may be 100%, 0%, or increments of t_c(HCO) with respect to the PWM period.
(4) Not production tested.
MIN MAX UNIT
25
ns
10 ns
Table 6-14. Timer and Capture Unit Timing Requirements^{(1) (2) (3)}
MIN MAX UNIT
t_w(TDIR)
t_w(CAP)
t_w(TCLKINL)
t_w(TCLKINH)
t_c(TCLKIN)
Pulse duration, TDIRx low/high
Without input qualifier
With input qualifier
Pulse duration, CAPx input low/high
Without input qualifier
With input qualifier
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
Cycle time, TCLKINx
2 × t_c(SCO)
1 × t_c(SCO) + IQT ⁽⁴⁾
2 × t_c(SCO)
1 x t_c(SCO) + IQT ⁽⁴⁾
40
40
4 × t_c(HCO)
cycles
cycles
60 %
60 %
ns
(1) The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling
period is 2n SYSCLKOUT cycles, where n is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the
qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples
are taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is
needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse
ensures reliable recognition.
(2) Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
(3) Not production tested.
(4) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × t_c(SCO)
XCLKOUT
(see Note A)
t_d(PWM)XCO
PWMx
A. XCLKOUT = SYSCLKOUT
t_w(PWM)
Figure 6-16. PWM Output Timing
XCLKOUT
(see Note A)
TDIRx
A. XCLKOUT = SYSCLKOUT
t_w(TDIR)
Figure 6-17. TDIRx Timing
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT
Electrical Specifications 105