SM320F2812-HT Datasheet, PDF (117/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
6.21 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-25 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-25. Relationship Between Parameters Configured in XTIMING and Duration of Pulse^{(1) (2) (3)}
DESCRIPTION
X2TIMING = 0
DURATION (ns)
X2TIMING = 1
LR
Lead period, read access
AR
Active period, read access
TR
Trail period, read access
LW
Lead period, write access
AW
Active period, write access
TW
Trail period, write access
XRDLEAD × t_c(XTIM)
(XRDACTIVE + WS + 1) × t_c(XTIM)
XRDTRAIL × t_c(XTIM)
XWRLEAD × t_c(XTIM)
(XWRACTIVE + WS + 1) x t_c(XTIM)
XWRTRAIL × t_c(XTIM)
(XRDLEAD × 2) × t_c(XTIM)
(XRDACTIVE × 2 + WS + 1) × t_c(XTIM)
(XRDTRAIL × 2) × t_c(XTIM)
(XWRLEAD × 2) × t_c(XTIM)
(XWRACTIVE × 2 + WS + 1) × t_c(XTIM)
(XWRTRAIL × 2) × t_c(XTIM)
(1) Not production tested.
(2) t_c(XTIM) – Cycle time, XTIMCLK
(3) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone's XTIMING register. These
requirements are in addition to any timing requirements as specified by that device's data sheet. No
internal device hardware is included to detect illegal settings.
• If the XREADY signal is ignored (USEREADY = 0), then:
1. Lead:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
Table 6-26. XTIMING Register Configuration Restrictions^{(1) (2)}
XRDLEAD
≥1
XRDACTIVE
≥0
XRDTRAIL
≥0
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XWRLEAD
≥1
XWRACTIVE
≥0
Examples of valid and invalid timing when
XWRTRAIL
≥0
not sampling
X2TIMING
0, 1
XREADY:
Table 6-27. Valid and Invalid Timing^{(1) (2)}
Invalid
Valid
XRDLEAD
0
1
XRDACTIVE
0
0
XRDTRAIL
0
0
XWRLEAD
0
1
XWRACTIVE
0
0
XWRTRAIL
0
0
X2TIMING
0, 1
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
• If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0),
then:
1. Lead:
2. Active:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
AR ≥ 2 × t_c(XTIM)
AW ≥ 2 × t_c(XTIM)
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Electrical Specifications 117