SM320F2812-HT Datasheet, PDF (93/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
6.10 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
4.0 pF
3.5 nH
1.85 pF
Transmission Line
Z0 = 50 Ω
(see note)
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-7. 3.3-V Test Load Circuit
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Electrical Specifications
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