SM320F2812-HT Datasheet, PDF (109/155 Pages) Texas Instruments – Digital Signal Processor

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XCLKOUT
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
GPIOxn
t_w(GPI)
Figure 6-23. General-Purpose Input Timing
NOTE
The pulse width requirement for general-purpose input is applicable for the XBIO and
ADCSOC pins as well.
6.19 SPI Master Mode Timing
Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)^{(1) (2) (3)}
NO.
1
2 ⁽⁴⁾
t_c(SPC)M
t_w(SPCH)M
t_w(SPCL)M
3 ⁽⁴⁾
t_w(SPCL)M
t_w(SPCH)M
4 ⁽⁴⁾
t_{d(SPCH-SIMO)M}
t_{d(SPCL-SIMO)M}
5 ⁽⁴⁾
t_{v(SPCL-SIMO)M}
t_{v(SPCH-SIMO)M}
8 ⁽⁴⁾
t_{su(SOMI-SPCL)M}
t_{su(SOMI-SPCH)M}
9 ⁽⁴⁾
t_{v(SPCL-SOMI)M}
t_{v(SPCH-SOMI)M}
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
SPI WHEN (SPIBRR + 1)
IS EVEN OR
SPIBRR = 0 OR 2
MIN
MAX
4t_c(LCO)
128t_c(LCO)
SPI WHEN (SPIBRR + 1)
IS ODD AND
SPIBRR > 3
MIN
5t_c(LCO)
UNIT
MAX
127t_c(LCO)
ns
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M 0.5t_c(SPC)M – 0.5t_c(LCO) – 10
0.5t_c(SPC)M 0.5t_c(SPC)M – 0.5t_c(LCO) – 10
0.5t_c(SPC)M – 0.5t_c(LCO)
ns
0.5t_c(SPC)M – 0.5t_c(LCO)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M 0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M 0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M + 0.5t_c(LCO)
ns
0.5t_c(SPC)M + 0.5t_c(LCO)
–10
10
–10
–10
10
–10
10
ns
10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
ns
0.5t_c(SPC)M – 10
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0
0
ns
0
0
0.25t_c(SPC)M – 10
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
ns
0.25t_c(SPC)M – 10
0.5t_c(SPC)M – 0.5t_c(LCO) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2)
t_c(SPC) + SPI clock
cycle time
+
LSPCLK
4
or
LSPCLK
(SPIBRR ) 1)
+
t_c(LCO) + LSPCLK cycle time
(3) Not production tested.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Electrical Specifications 109