SM320F2812-HT Datasheet, PDF (18/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
www.ti.com
NAME
XMP/MC
XHOLD
XHOLDA
XZCS0AND1
XZCS2
XZCS6AND7
XWE
XRD
XR/W
XREADY
PIN NO.
172-PIN
HFG
17
155
80
43
86
130
82
41
50
157
Table 2-3. Signal Descriptions ⁽¹⁾ (continued)
DIE PAD
NO.
DIE PAD
X-CENTER
(mm)
23
2308.2
174
42.6
93
5361.5
50
5148.5
100
5361.5
146
42.6
95
5361.5
48
4900.6
57
5361.5
176
42.6
DIE PAD
Y-CENTER
(mm)
42.6
2157.6
4137.4
42.6
4844.2
4888.6
4347.5
42.6
755.0
1972.4
I/O/Z⁽²⁾ PU/PD⁽³⁾
DESCRIPTION
Microprocessor/Microcomputer Mode
Select. Switches between microprocessor
and microcomputer mode. When high,
Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the
I
PD external interface and on-chip boot ROM
may be accessed instead. This signal is
latched into the XINTCNF2 register on a
reset and the user can modify this bit in
software. The state of the XMP/MC pin is
ignored after reset.
External Hold Request. XHOLD, when
active (low), requests the XINTF to release
the external bus and place all buses and
I
PU strobes into a high-impedance state. The
XINTF releases the bus when any current
access is complete and there are no
pending accesses on the XINTF.
External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
O/Z
–
and strobe signals are in a high-impedance
state. XHOLDA is released when the
XHOLD signal is released. External devices
should only drive the external bus when
XHOLDA is active (low).
XINTF Zone 0 and Zone 1 Chip Select.
O/Z
–
XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is
performed.
XINTF Zone 2 Chip Select. XZCS2 is active
O/Z
–
(low) when an access to the XINTF Zone 2
is performed.
XINTF Zone 6 and Zone 7 Chip Select.
O/Z
–
XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is
performed.
Write Enable. Active-low write strobe. The
O/Z
–
write strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
O/Z
–
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
NOTE: The XRD and XWE signals are
mutually exclusive.
Read Not Write Strobe. Normally held high.
O/Z
–
When low, XR/W indicates write cycle is
active; when high, XR/W indicates read
cycle is active.
Ready Signal. Indicates peripheral is ready
to complete the access when asserted to 1.
I
PU XREADY can be configured to be a
synchronous or an asynchronous input.
See the timing diagrams for more details.
18
Introduction
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