SM320F2812-HT Datasheet, PDF (133/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)^{(1) (2) (3) (4)}
MIN
MAX UNIT
t_d(HL-HiZ)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
4t_c(XTIM) + t_c(XCO)
ns
4t_c(XTIM) + 2t_c(XCO)
ns
4t_c(XTIM)
ns
6t_c(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
(4) Not production tested.
See Note A
See Note B
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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Electrical Specifications 133