SM320F2812-HT Datasheet, PDF (19/155 Pages) Texas Instruments – Digital Signal Processor

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NAME
X1/XCLKIN
X2
XCLKOUT
TESTSEL
XRS
TEST1
TEST2
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
PIN NO.
172-PIN
HFG
75
74
117
131
156
66
65
Table 2-3. Signal Descriptions ⁽¹⁾ (continued)
DIE PAD
NO.
88
87
132
147
175
76
75
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
I/O/Z⁽²⁾ PU/PD⁽³⁾
DESCRIPTION
JTAG AND MISCELLANEOUS SIGNALS
5361.5
3668.7
I
5361.5
3582.6
O
1701.2
5057.5
O
–
42.6
4764.6
I
PD
42.6
2077.8
I/O
PU
5361.5
2522.3
I/O
–
5361.5
2436.1
I/O
–
Oscillator Input – input to the internal
oscillator. This pin is also used to feed an
external clock. The 28× can be operated
with an external clock source, provided that
the proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the
X1/XCLKIN pin is referenced to the 1.8-V
(or 1.9-V) core digital power supply (V_DD),
rather than the 3.3-V I/O supply (V_DDIO). A
clamping diode may be used to clamp a
buffered clock signal to ensure that the
logic-high level does not exceed V_DD
(1.8 V or 1.9 V) or a 1.8-V oscillator may be
used.
Oscillator Output
Output clock derived from SYSCLKOUT to
be used for external wait-state generation
and as a general-purpose clock source.
XCLKOUT is either the same frequency,
1/2 the frequency, or 1/4 the frequency of
SYSCLKOUT. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can
be turned off by setting bit 3 (CLKOFF) of
the XINTCNF2 register to 1.
Test Pin. Reserved for TI. Must be
connected to ground.
Device Reset (in) and Watchdog Reset
(out).
Device reset. XRS causes the device to
terminate execution. The PC points to the
address contained at the location
0x3FFFC0. When XRS is brought to a high
level, execution begins at the location
pointed to by the PC. This pin is driven low
by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is
driven low for the watchdog reset duration
of 512 XCLKIN cycles.
The output buffer of this pin is an
open-drain with an internal pullup (100 mA,
typical). It is recommended that this pin be
driven by an open-drain device.
Test Pin. Reserved for TI. On F281x
devices, TEST1 must be left unconnected.
Test Pin. Reserved for TI. On F281x
devices, TEST2 must be left unconnected.
Copyright © 2009–2010, Texas Instruments Incorporated
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Introduction
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