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SM320F2812-HT Datasheet, PDF (69/155 Pages) Texas Instruments – Digital Signal Processor | |||
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SM320F2812-HT
www.ti.com
SGUS062A â JUNE 2009 â REVISED APRIL 2010
4.5 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
⢠Compatible to McBSP in TMS320C54xâ¢/ TMS320C55x⢠DSP devices, except the DMA features
⢠Full-duplex communication
⢠Double-buffered data registers which allow a continuous data stream
⢠Independent framing and clocking for receive and transmit
⢠External shift clock generation or an internal programmable frequency shift clock
⢠A wide selection of data sizes including 8/12/16/20/24 or 32-bits
⢠8-bit data transfers with LSB or MSB first
⢠Programmable polarity for both frame synchronization and data clocks
⢠Highly programmable internal clock and frame generation
⢠Support A-bis mode
⢠Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
⢠Works with SPI-compatible devices
⢠Two 16 x 16-level FIFO for Transmit channel
⢠Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
⢠T1/E1 framers
⢠MVIP switching-compatible and ST-BUS-compliant devices including:
â MVIP framers
â H.100 framers
â SCSA framers
â IOM-2 compliant devices
â AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
â IIS-compliant devices
CLKSRG
McBSP clock rate = CLKG =
,
â¢
1+ CLKGDIV
where CLKSRG source could be LSPCLK, CLKX, or CLKR.(2)
(2) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is
less than the I/O buffer speed limitâ20-MHz maximum.
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