SM320F2812-HT Datasheet, PDF (96/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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See Note A
See Note B
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-8. Clock Timing
6.14 Reset Timing
Table 6-9. Reset (XRS) Timing Requirements^{(1) (2)}
MIN
NOM MAX UNIT
t_w(RSL1)
t_w(RSL2)
t_w(WDRS)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Warm reset
WD-initiated reset
8t_c(CI)
8t_c(CI)
512t_c(CI)
512t_c(CI)
cycles
cycles
cycles
t_d(EX)
t_OSCST ⁽³⁾
t_su(XPLLDIS)
t_h(XPLLDIS)
t_h(XMP/MC)
t_h(boot-mode)
Delay time, address/data valid after XRS high
Oscillator start-up time
Setup time for XPLLDIS pin
Hold time for XPLLDIS pin
Hold time for XMP/MC pin
Hold time for boot-mode pins
1
16t_c(CI)
16t_c(CI)
16t_c(CI)
2520t_c(CI) ⁽⁴⁾
32t_c(CI)
10
cycles
ms
cycles
cycles
cycles
cycles
(1) If external oscillator/clock source isused, reset time has to be low at least for 1 ms after V_DD reaches 1.5 V.
(2) Not production tested.
(3) Dependent on crystal/resonator and board design.
(4) The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x Boot ROM Reference Guide (literature number SPRU095) and TMS320x281x System Control and Interrupts Reference
Guide (literature number SPRU078) for further information.
96
Electrical Specifications
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