SM320F2812-HT Datasheet, PDF (70/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of
Peripheral Frame 2.
Peripheral Write Bus
MXINT
To CPU
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
LSPCLK
McBSP Registers
and Control Logic
TX FIFO
Interrupt
TX FIFO _15
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
16
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
Compand Logic
XSR2
XSR1
McBSP
McBSP Receive
Interrupt Select Logic
MRINT
To CPU
RX Interrupt Logic
RSR2
16
RBR2 Register
16
RSR1
16
Expand Logic
RBR1 Register
16
DRR2 Receive Buffer DRR1 Receive Buffer
16
16
RX FIFO
Interrupt
RX FIFO _15
RX FIFO _15
—
—
RX FIFO _1
RX FIFO _1
RX FIFO _0
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
Figure 4-9. McBSP Module With FIFO
FSX
CLKX
DX
DR
CLKR
FSR
70
Peripherals
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