SM320F2812-HT Datasheet, PDF (147/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)⁽¹⁾
NO.
M49 t_su(DRV-CKXH)
Setup time, DR valid before CLKX high
M50 t_h(CKXH-DRV)
Hold time, DR valid after CLKX high
M51 t_su(FXL-CKXL)
Setup time, FSX low before CLKX low
M52 t_c(CKX)
Cycle time, CLKX
(1) Not production tested.
MASTER
MIN MAX
P – 10
P – 10
2P
SLAVE
MIN MAX
8P – 10
8P – 10
8P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)^{(1) (2)}
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
M43 t_h(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44 t_d(FXL-CKXL)
Delay time, FSX low to CLKX low
P
ns
M47 t_{dis(FXH-DXHZ)}
Disable time, DX high impedance following last data bit from FSX
high
6
6P + 6
ns
M48 t_d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
CLKX
LSB
M51
MSB
M52
M43
M44
FSX
M47
M48
DX
Bit 0
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Electrical Specifications 147