SM320F2812-HT Datasheet, PDF (37/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 3-4. Peripheral Frame 0 Registers⁽¹⁾
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE⁽²⁾
Device Emulation Registers
0x00 0880
0x00 09FF
384
EALLOW protected
reserved
0x00 0A00
0x00 0A7F
128
FLASH Registers⁽³⁾
0x00 0A80
0x00 0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x00 0AE0
0x00 0AEF
16
EALLOW protected
reserved
0x00 0AF0
0x00 0B1F
48
XINTF Registers
0x00 0B20
0x00 0B3F
32
Not EALLOW protected
reserved
0x00 0B40
0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00
0x00 0C3F
64
Not EALLOW protected
reserved
0x00 0C40
0x00 0CDF
160
PIE Registers
0x00 0CE0
0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00
0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00
0x00 0FFF
512
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-5. Peripheral Frame 1 Registers⁽¹⁾
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE
eCAN Registers
0x00 6000
0x00 60FF
256
(128 × 32)
Some eCAN control registers (and selected bits in
other eCAN control registers) are EALLOW-protected.
eCAN Mailbox RAM
0x00 6100
0x00 61FF
256
(128 × 32)
Not EALLOW-protected
reserved
0x00 6200
0x00 6FFF
3584
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
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