SM320F2812-HT Datasheet, PDF (140/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on
two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels are sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
ADC Event Trigger from
EV or Other Sources
Sample n
Sample n+1
Sample n+2
t_d(SH)
t_SH
t_{dschA0_n+1}
t_{dschA0_n}
t_{dschB0_n}
t_{dschB0_n+1}
Figure 6-40. Simultaneous Sampling Mode Timing
t_d(SH)
t_SH
t_{d(schA0_n)}
t_{d(schB0_n)}
t_{d(schA0_n+1)}
Table 6-51. Simultaneous Sampling Mode Timing⁽¹⁾
Delay time from event
trigger to sampling
Sample/Hold
width/Acquisition Width
Delay time for first result
to appear in Result
register
Delay time for first result
to appear in Result
register
Delay time for successive
results to appear in Result
register
SAMPLE n
2.5t_c(ADCCLK)
(1 + Acqps) ×
t_c(ADCCLK)
4t_c(ADCCLK)
5t_c(ADCCLK)
SAMPLE n + 1
AT 25-MHz ADC
CLOCK,
t_c(ADCCLK) = 40 ns
REMARKS
40 ns with Acqps = 0
Acqps value = 0–15
ADCTRL1[8:11]
160 ns
(3 + Acqps) ×
t_c(ADCCLK)
200 ns
120 ns
(1) Not production tested.
140 Electrical Specifications
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