SM320F2812-HT Datasheet, PDF (104/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush perperly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT
mode and consumes absolute minimum power.
D. When XNMI is friven active (negative edge triggered shown, as an example), the oscillator is turned on; but the PLL is
not activiated.
E. When XNMI is deactiveted, it initiates the PLL lock sequence, which takes 131, 072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device responds to the interrupt (if enabled), after a latency. The HALT mode
is now exited.
G. Normal operation resumes.
H. XCLKOUT = SYSCLKOUT
Figure 6-15. HALT Wakeup Using XNMI
6.16 Event Manager Interface
6.16.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
104 Electrical Specifications
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