SM320F2812-HT Datasheet, PDF (115/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)^{(1) (2) (3)}
NO.
MIN
12
13 ⁽⁴⁾
14 ⁽⁴⁾
17 ⁽⁴⁾
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
t_w(SPCL)S
t_w(SPCH)S
t_{su(SOMI-SPCH)S}
t_{su(SOMI-SPCL)S}
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity =
0)
Setup time, SPISOMI before SPICLK low (clock polarity =
1)
8tc(LCO)
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.125t_c(SPC)S
0.125t_c(SPC)S
18 ⁽⁴⁾
t_{v(SPCH-SOMI)S}
t_{v(SPCL-SOMI)S}
Valid time, SPIS OMI data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
0.75t_c(SPC)S
0.75t_c(SPC)S
21 ⁽⁴⁾
t_{su(SIMO-SPCH)S}
Setup time, SPISIMO before SPICLK high (clock polarity =
0)
0
t_{su(SIMO-SPCL)S}
Setup time, SPISIMO before SPICLK low (clock polarity =
1)
0
22 ⁽⁴⁾
tv_(SPCH-SIMO)S
t_{v(SPCL-SIMO)S}
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5t_c(SPC)S
0.5t_c(SPC)S
(1) The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
(2)
t_c(SPC) + SPI clock
cycle time
+
LSPCLK
4
or
LSPCLK
(SPIBRR ) 1)
+
t_c(LCO) + LSPCLK cycle time
(3) Not production tested.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
MAX
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
12
13
14
17
18
SPISOMI
SPISOMI Data Is Valid
Data Valid
SPISIMO
21
22
SPISIMO Data
Must Be Valid
SPISTE
(see Note A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-27. SPI Slave Mode External Timing (Clock Phase = 1)
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Electrical Specifications 115