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SM320F2812-HT Datasheet, PDF (97/155 Pages) Texas Instruments – Digital Signal Processor
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VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
(See Note B)
VDD, VDD1
(1.8 V (or 1.9 V))
XCLKIN
2.5 V
0.3 V
X1
SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
XCLKOUT
XRS
Address/Data/
Control
XF/XPLLDIS
XCLKIN/8 (See Note C)
tOSCST
tw(RSL1)
User-Code Dependent
Address/Data Valid. Internal Boot-ROM Code Execution Phase
td(EX)
tsu(XPLLDIS)
XPLLDIS Sampling
(Don’t Care)
User-Code Execution Phase
User-Code Dependent
th(XPLLDIS)
GPIOF14
XMP/MC
th(XMP/MC)
(Don’t Care)
Boot-Mode Pins
See Note A
th(boot-mode)
(See Note D)
GPIO Pins as Input
Boot-ROM Execution Starts
User-Code Dependent
Peripheral/GPIO Function
Based on Boot Code
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V.
B. VDDAn − VDDA1/VDDA2 and AVDDREFBG
C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution
time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.
Figure 6-9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)
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