SM320F2812-HT Datasheet, PDF (74/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
www.ti.com
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.
Table 4-8. SCI-A Registers⁽¹⁾
NAME
ADDRESS
SCICCRA
0x00 7050
SCICTL1A
0x00 7051
SCIHBAUDA
0x00 7052
SCILBAUDA
0x00 7053
SCICTL2A
0x00 7054
SCIRXSTA
0x00 7055
SCIRXEMUA
0x00 7056
SCIRXBUFA
0x00 7057
SCITXBUFA
0x00 7059
SCIFFTXA
0x00 705A
SCIFFRXA
0x00 705B
SCIFFCTA
0x00 705C
SCIPRIA
0x00 705F
(1) Shaded registers are new registers for the FIFO mode.
SIZE (×16)
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
Table 4-9. SCI-B Registers^{(1) (2)}
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
SCICCRB
0x00 7750
1
SCI-B Communications Control Register
SCICTL1B
0x00 7751
1
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
1
SCI-B Control Register 2
SCIRXSTB
0x00 7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB
0x00 775A
1
SCI-B FIFO Transmit Register
SCIFFRXB
0x00 775B
1
SCI-B FIFO Receive Register
SCIFFCTB
0x00 775C
1
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
1
SCI-B Priority Control Register
(1) Shaded registers are new registers for the FIFO mode.
(2) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
74
Peripherals
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT