SM320F2812-HT Datasheet, PDF (79/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
4.8 GPIO MUX
The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pins
can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the
GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction
(via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL)
registers). Table 4-11 lists the GPIO Mux Registers.
Table 4-11. GPIO Mux Registers^{(1) (2) (3)}
NAME
ADDRESS
SIZE (×16)
REGISTER DESCRIPTION
GPAMUX
0x00 70C0
1
GPIO A Mux Control Register
GPADIR
0x00 70C1
1
GPIO A Direction Control Register
GPAQUAL
0x00 70C2
1
GPIO A Input Qualification Control Register
reserved
0x00 70C3
1
GPBMUX
0x00 70C4
1
GPIO B Mux Control Register
GPBDIR
0x00 70C5
1
GPIO B Direction Control Register
GPBQUAL
0x00 70C6
1
GPIO B Input Qualification Control Register
reserved
0x00 70C7
1
reserved
0x00 70C8
1
reserved
0x00 70C9
1
reserved
0x00 70CA
1
reserved
0x00 70CB
1
GPDMUX
0x00 70CC
1
GPIO D Mux Control Register
GPDDIR
0x00 70CD
1
GPIO D Direction Control Register
GPDQUAL
0x00 70CE
1
GPIO D Input Qualification Control Register
reserved
0x00 70CF
1
GPEMUX
0x00 70D0
1
GPIO E Mux Control Register
GPEDIR
0x00 70D1
1
GPIO E Direction Control Register
GPEQUAL
0x00 70D2
1
GPIO E Input Qualification Control Register
reserved
0x00 70D3
1
GPFMUX
0x00 70D4
1
GPIO F Mux Control Register
GPFDIR
0x00 70D5
1
GPIO F Direction Control Register
reserved
0x00 70D6
1
reserved
0x00 70D7
1
GPGMUX
0x00 70D8
1
GPIO G Mux Control Register
GPGDIR
0x00 70D9
1
GPIO G Direction Control Register
reserved
0x00 70DA
1
reserved
0x00 70DB
1
reserved
0x00 70DC
0x00 70DF
4
(1) Reserved locations returns undefined values and writes is ignored.
(2) Not all inputs support input signal qualification.
(3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
If configured for Digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual
I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the
GPxDAT registers). Table 4-12 lists the GPIO Data Registers. For more information, see the
TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078).
Copyright © 2009–2010, Texas Instruments Incorporated
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