SM320F2812-HT Datasheet, PDF (142/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.30 Multichannel Buffered Serial Port (McBSP) Timing
6.30.1 McBSP Transmit and Receive Timing
Table 6-52. McBSP Timing Requirements^{(1) (2) (3)}
NO.
MIN
MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1
kHz
20⁽⁴⁾ MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range
50
ns
1 ms
M11
M12
M13
M14
t_c(CKRX)
t_w(CKRX)
t_r(CKRX)
t_f(CKRX)
M15 t_su(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
2P
ns
P–7
ns
7 ns
7 ns
18
ns
2
M16 t_h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
0
ns
CLKR ext
6
M17 t_su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
18
ns
CLKR ext
2
M18 t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
0
ns
CLKR ext
6
CLKX int
18
M19 t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
2
ns
M20 t_h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
0
ns
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the
timing references of that signal are also inverted.
(2)
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux.
CLKG
+
CLKSRG
(1 ) CLKGDV)
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching
speed.
(3) Not production tested.
(4) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
142 Electrical Specifications
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