SM320F2812-HT Datasheet, PDF (132/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.28 XHOLD/XHOLDA Timing
Table 6-44. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)^{(1) (2) (3)}
MIN
MAX UNIT
t_{d(HL–HiZ)}
t_{d(HL–HAL)}
t_{d(HH–HAH)}
t_{d(HH–BV)}
Delay time, XHOLD low to Hi–Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
4t_c(XTIM)
ns
5t_c(XTIM)
ns
3t_c(XTIM)
ns
4t_c(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) Not production tested.
XCLKOUT
(/1 Mode)
XHOLD
XHOLDA
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
t_d(HL-Hiz)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
High-Impedance
XA[18:0]
Valid
High-Impedance
Valid
XD[15:0]
Valid
See Note A
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-35. External Interface Hold Waveform
See Note B
132 Electrical Specifications
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