SM320F2812-HT Datasheet, PDF (48/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
3.8 OSC and PLL Block
Figure 3-7 shows the OSC and PLL block on the F2812.
XF_XPLLDIS
Latch
XPLLDIS
XCLKIN
X1/XCLKIN
XRS
OSCCLK (PLL Disabled)
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-Bit PLL Select
X2
PLL
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0
CLKIN
CPU
1
SYSCLKOUT
4-Bit PLL Select
PLL Block
Figure 3-7. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1/XCLKIN
and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the
X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed
V_DD. The PLLCR bits [3:0] set the clocking ratio.
Table 3-14. PLLCR Register Bit Definitions
BIT(S) NAME
TYPE
XRS RESET⁽¹⁾
DESCRIPTION
15:04 reserved
R=0
0:00
SYSCLKOUT = (XCLKIN x n)/2, where n is the PLL multiplication factor.
Bit Value
n
SYSCLKOUT
3:00
DIV
R/W
0,0,0,0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN × 1.5
XCLKIN × 2
XCLKIN × 2.5
XCLKIN × 3
XCLKIN × 3.5
XCLKIN × 4
XCLKIN × 4.5
XCLKIN × 5
Reserved
Reserved
Reserved
Reserved
Reserved
(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not
changed.
48
Functional Overview
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