SM320F2812-HT Datasheet, PDF (112/155 Pages) Texas Instruments – Digital Signal Processor

SM320F2812-HT
SGUS062A – JUNE 2009 – REVISED APRIL 2010
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
6
7
Master Out Data Is Valid
10
11
Master In Data
Must Be Valid
www.ti.com
3
Data Valid
SPISTE
(see Note A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-25. SPI Master External Timing (Clock Phase = 1)
112 Electrical Specifications
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F2812-HT